With the development trend of ultra-large scale integrated circuits, the feature size of integrated circuits continues to decrease, and the requirements for packaging technology of integrated circuits are correspondingly increasing. Existing packaging technologies involve ball grid array (BGA), chip scale package (CSP), wafer-level package (WLP), 3D package (3D) and system in package (System in Package, SiP), etc.
At present, to meet the goal for lower cost, more reliability, and faster and higher density of integrated circuit packaging, advanced packaging methods mainly use wafer-level system-in-package (WLSiP). Compared with the conventional SiP, the WLSiP completes the packaging integration process on a wafer, which has the advantages of greatly reducing the area of the package structure, reducing the manufacturing cost, optimizing the electrical performance, batch manufacturing, etc., therefore can significantly reduce workload and needs for equipment.
The WLSiP mainly includes two important processes: physical connection and electrical connection. For example, a bonding process is used to realize the physical connection between chips to be integrated and a wafer, the electrical connection between semiconductor devices is realized by an electroplating technology, and the electrical connection between the chips and an external circuit is realized through through-silicon via (TSV).
However, the electrical connections in current WLSiP needs to be simplified.